1. Field of the Invention
The present invention relates to a semiconductor fabrication method, and, more particularly, to a method for fabricating a die seal structure around a chip die for preventing the internal circuit of the chip die from lateral stress induced during the period of cutting wafers.
2. Description of the Related Art
In the semiconductor process, a plurality of dies, each of which contains an integrated circuit, are fabricated on a semiconductor wafer at a time. Scribe lines are provided between every two adjacent dies so that the dies can be separated by cutting the semiconductor wafer along these scribe lines.
However, when a wafer is cut into a plurality of dies, lateral stress is induced, thereby affecting the internal circuits via the structure of the IC. Consequently, microcracking may occur which can affect the production yield. One approach for solving such a problem is to form a die seal structure between the scribe line and the peripheral region of the internal circuit. Therefore, stress induced by cutting wafers is generally blocked by the die seal and will not directly affect the internal circuit of a die. FIG. 1 shows a top view of a chip die. It should be noticed that all subsequent figures are not to scale. The die seal is directed to the structure between internal circuit 2 and scribe line 10. The die seal structure comprises buffer area 4, seal ring 6 and buffer space 8. Seal ring 6, which is a stacked structure comprising metal layers and dielectric layers, is usually formed together with buffer area 4 and buffer space 8 in the multi-metal interconnection process. The dielectric layer of the buffer space 8 is made of SiO.sub.2.
FIG. 2 (PRIOR ART) and FIG. 3 (PRIOR ART) illustrate two cross-sectional views of the conventional die seal structures, respectively. It should be notified that the die seal structures shown in FIG. 2 and FIG. 3 are formed together with a triple-metal interconnection process. Now referring to FIG. 2, the whole structure is formed on silicon substrate 1. Field oxide 20 is used as an isolation structure and also can be used to separate a die seal structure (comprising buffer area 4, seal ring 6 and buffer space 8) and internal circuit 2. Seal ring 6 comprises three dielectric layers 610, 612 and 614, wherein dielectric layer 612 is formed over dielectric layer 610, and dielectric layer 614 is formed over dielectric layer 612. Each of dielectric layers 610, 612 and 614 is covered with metal layers 611, 613 and 615, respectively, which are formed together with the triple-metal process. Finally, passivation layer 616 is formed and covers all the dielectric layers and the metal layers. In summary, seal ring 6 of conventional die seal structure shown in FIG. 2 is produced by alternately depositing the dielectric layers and the metal layers. It should be noted that these dielectric layers and metal layers are formed during the common semiconductor process and do not require extra steps. In general, seal ring 6 has a width of about 20 .mu.m, buffer area 4 between internal circuit 2 and seal ring 6 has a width of about 25 .mu.m, and buffer space 8 between seal ring 6 and the scribe line has a width of about 5.about.10 .mu.m.
The die seal structure shown in FIG. 3 is quite similar to that shown in FIG. 2, except in the following aspects. In FIG. 3, seal ring 6 includes three metal layers 621, 623 and 625, as in FIG. 2, and further includes metal plugs 631, 633 and 635, located between these metal layers. In this seal ring structure, metal layers 621, 623 and 625 and metal plugs 631, 633, 635 are also formed during the common metalization and plug process and do not require extra steps. Therefore, metal plugs 631, 633 and 635 are usually made of tungsten or aluminum. Such a seal ring structure is utilized in the die seal structure to enhance robustness to sawing stress, thereby preventing the internal circuit from damage.
In the development of process techniques, a technique called global planarization is commonly utilized. The most common one is CMP(chemical-mechanical polishing). When CMP is utilized in the fabrication process of semiconductors, the protection ability of the die seal may be reduced. The reason for this will be discussed in the following detailed description. When an inter-metal dielectric layer is planarized by using CMP, the dielectric layer between seal ring 6 and scribe line 10 may not be completely removed in the etching of the contact window and metal via and passivation, and may accumulate continually on the buffer space. Dielectric material 81 shown in FIG. 2 and dielectric layer 82 shown in FIG. 3 on the buffer space 8 may have a depth of about 12000 .ANG. in the prior art. The residual dielectric material on buffer space 8 may be a path of stress when a wafer is sawed. Thereby, the reliability of the dies may be reduced.